Modelling the Failure Time of a Transistor

Authors

  • Marcelo Pereira Fernandes Júnior Universidade Federal dos Vales do Jequitinhonha e Mucuri
  • Marcos Henrique Palma Lopes Universidade Federal dos Vales do Jequitinhonha e Mucuri
  • Paulo César de Resende Andrade Instituto de Ciência e Tecnologia - ICT Universidade Federal dos Vales do Jequitinhonha e Mucuri - UFVJM http://orcid.org/0000-0002-7865-8174

DOI:

https://doi.org/10.5752/P.2316-9451.2019v7n3p79-90

Keywords:

Curve of the bathtub. Reliability. Senile Mortality. Weibull distribution.

Abstract

The present work aims to model the life span of a transistor through parametric reliability analysis. The application of reliability techniques allows the description of the behavior of equipment failures. The research method consisted of a case study based on the collected failure time of 24 transistors. Graphical and analytical methods, through the ProConf software, were used to verify that the Weibull distribution is the one that best fits the data. The reliability and risk functions are presented. The increasing risk and decreasing reliability, associated with the fact that the parameter is greater than one, indicates equipment wear. This corresponds to the onset of senile mortality, the final phase of its useful life.

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Author Biographies

Marcelo Pereira Fernandes Júnior, Universidade Federal dos Vales do Jequitinhonha e Mucuri

Graduando em Ciência e Tecnologia pela Universidade Federal dos Vales do Jequitinhonha e Mucuri

Marcos Henrique Palma Lopes, Universidade Federal dos Vales do Jequitinhonha e Mucuri

Graduando em Ciência e Tecnologia pela Universidade Federal dos Vales do Jequitinhonha e Mucuri

Paulo César de Resende Andrade, Instituto de Ciência e Tecnologia - ICT Universidade Federal dos Vales do Jequitinhonha e Mucuri - UFVJM

Professor Adjunto II do Instituto de Ciência e Tecnologia da Universidade Federal dos Vales do Jequitinhonha e Mucuri

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Published

2019-11-29

How to Cite

FERNANDES JÚNIOR, Marcelo Pereira; LOPES, Marcos Henrique Palma; ANDRADE, Paulo César de Resende. Modelling the Failure Time of a Transistor. Abakós, Belo Horizonte, v. 7, n. 3, p. 79–90, 2019. DOI: 10.5752/P.2316-9451.2019v7n3p79-90. Disponível em: https://periodicos.pucminas.br/abakos/article/view/19375. Acesso em: 10 sep. 2025.

Issue

Vol. 7 No. 3 (2019)

Section

Artigos completos / Full papers

License

I  (we) submit the present work, an original and unpublished manuscript, from my (our) authorship, to Abakós - Magazine of Interdisciplinary Studies on Science and Informatics, and  I (we) agree that the copyright related to this work will become property of  PUC Minas Publisher. No partial or full reproduction is allowed, by any means (printed or electronic), dissociated from Abakós. Any reproduction requires prior written authorization granted by the Editor.

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